This invention relates generally to the testing of electrical circuits, and more particularly, the invention relates to the probe testing of integrated die in a semiconductor wafer.
Semiconductor integrated circuits are fabricated in a batch process where a plurality of identical integrated circuits are formed in a single wafer of silicon. Prior to scribing and breaking the wafer into individual integrated circuit die, each of the circuits is electrically tested so that defective circuits can be marked and subsequently discarded.
Heretofore, electrical parametric testers have tested die serially because it is easier and most test times are short enough to allow serial testing of individual circuits. As shown in FIGS. 1A, 1B, the conventional tester includes a probe card which is essentially a small printed circuit board 10 with a hole 12 through which needle probes 14 extend to engage contacts on an integrated circuit. The printed circuit board traces 16 electrically connect the probes to the tester. See for example, U.S. Pat. No. 3,613,001. The probe needles access bonding pads 20 of a die 22 on a wafer 24, as illustrated in FIG. 2.
However, some integrated circuits require test times not measured in seconds or minutes, but rather in days, weeks, or months. The serial testing of such individual die is not feasible. Printed circuit probe cards with multiple openings for needle probes have been proposed for testing these integrated circuits, but such cards have problems of alignment and planarity.
The bond pads which the probes are contacting are typically no larger than 100 .mu.m on the side. Needle probes have a tendency to move slightly through repeated use. This can cause the probes to become misaligned with respect to each other and with respect to the bond pads on the wafer. This is a sizable problem with conventional probe cards. The problem is compounded many times over when the spacing between the probes becomes very large as when multiple die are probed simultaneously from the same probe card.
Further, all the probes must extend downwardly from the probe card the same distance with the tips in one plane. However, the probes have a tendency to go out of planarity which results in some probes making contact with the wafer, and some not. In addition, this problem is acerbated by temperature which is a common testing requirement. Again, this is a major problem within one die, but is compounded many times over when the spacing between probes becomes large, as when multiple die are being probed simultaneously.
Wedge cards were introduced within the past few years as a means of accessing multiple dies on a wafer simultaneously. These cards address both the issue of alignment and planarity. The wedge cards are small (i.e., 1".times.1") probe cards suspended on the arm of an X,Y,Z manipulator. The wedge card typically has up to 20 needle probes with a wire cable attached thereto to bring the test signals in and out. The probes all extend from one side or edge of the wedge card. The manipulator allows precise movement in the X,Y and Z axes, and by using multiple manipulators, the user can independently probe several die simultaneously on a wafer as illustrated in FIG. 3. Because each manipulator has independent control of X, Y, and Z motions, the issues of alignment and planarity are limited to the dimensions of the individual wedge card, and not to the distance between them. However, even with this approach a limited number of wedge cards and manipulators can be used simultaneously. A primary problem is physically fitting the manipulators and wedge cards around the wafer, which limits the simultaneous testing to a maximum of eight die.
The present invention is directed to a new apparatus and method for simultaneously testing multiple integrated circuits on a semiconductor wafer.